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covered-doc: Verilog code coverage analysis tool - documentation

Distribution Debian testing
Abteilung doc
Quelle covered
Version 0.7.8-2
Maintainer Debian Electronics Team <pkg-electronics-devel@lists.alioth.debian.org>
Beschreibung Covered is a Verilog code coverage utility that reads in a Verilog design and
a generated VCD/LXT dumpfile from that design and generates a coverage file
that can be merged with other coverage files or used to create a coverage
report. Covered also contains the GUI coverage report utility that reads in a
coverage file to allow interactive coverage discovery. Areas of coverage
measured by Covered are: line, toggle, memory, combinational logic, FSM
state/state-transition and assertion coverage.
.
This package contains the documentation.
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